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integrated video filter with selectable cutoff frequencies for rgb, hd/sd y, c, and cv aDA4410-6 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 analog devices, inc. all rights reserved. features sixth-order filters with selectable cutoff frequencies 36 mhz, 18 mhz, 9 mhz many video standards supported rgb/ypbpr/yuv/sd/yc/cv ideal for resolutions up to 1080i ?1 db bandwidth of 30 mhz for hd 2:1 multiplexers on all inputs selectable gain: 2 or 4 dc output offset adjust: 0.5 v, input referred excellent video specifications ntsc differential gain: 0.11% ntsc differential phase: 0.25 low input bias current: 6.6 a wide supply range: +4.5 v to 5 v rail-to-rail output typical output swing of 4.5 v p-p on single 5 v supply disable feature applications set-top boxes dvd players and recorders hdtvs general description the aDA4410-6 is a comprehensive integrated filtering solution that is carefully designed to give designers the flexibility to easily filter and drive many types of video signals, including high definition video. in the rgb/component channels, the cutoff frequencies of the sixth-order filters can be selected by two logic pins to obtain four filter combinations that are tuned for rgb, high definition, and standard definition video. cutoff frequencies range from 9 mhz to 36 mhz. the aDA4410-6 also provides filtering for the legacy standard s-video and composite video signals. with a differential gain of 0.11% and a differential phase of 0.25, the aDA4410-6 is an excellent choice for any composite video (cv) application. the aDA4410-6 offers gain and output offset voltage adjustments. with a single logic pin, the gain of the part can be selected to be 2 or 4. output offset voltage is continuously adjustable over an input-referred range of 500 mv by applying a differential voltage to an independent offset control input. functional block diagram 36mhz, 18mhz, 9mhz 36mhz, 18mhz, 9mhz 36mhz, 18mhz, 9mhz 9mhz 9mhz y1/g1 in y2/g2 in 2 4 y/g out pb1/b1 in pb2/b2 in 2 4 pb/b out pr1/r1 in pr2/r2 in level1 dc offset hd input select level2 cutoff select gain select 2 4 pr/r out y1 in y2 in 2 4 y out c1 in c2 in sd input select disable 2 4 c out 2 cv out 2 aDA4410-6 05265-001 figure 1. the aDA4410-6 offers 2:1 multiplexers on its inputs that can be used in applications where multiple sources of video exist. the aDA4410-6 can operate on a single +5 v supply as well as 5 v supplies. single-supply operation is ideal for applications where power consumption is critical. the disable feature allows for further power conservation by reducing the supply current to typically 15 a when a particular device is not in use. dual-supply operation is best for applications where the negative-going excursions of the signal must swing at or below ground while maintaining excellent video performance. the output buffers have the ability to drive two 75 doubly terminated cables that are either dc- or ac-coupled. the aDA4410-6 is available in a 32-lead lfcsp and operates in the extended industrial temperature range of ?40c to +85c.
aDA4410-6 rev. b | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 7 thermal resistance ...................................................................... 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 12 applications ..................................................................................... 13 overview ..................................................................................... 13 multiplexer select inputs ........................................................... 13 throughput gain ........................................................................ 13 disable ......................................................................................... 13 cutoff frequency selection ....................................................... 13 output dc offset control ........................................................ 13 input and output coupling ...................................................... 14 printed circuit board layout ................................................... 15 video encoder reconstruction filter ...................................... 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 3/06rev. a to rev. b changes to table 1............................................................................ 3 changes to table 2............................................................................ 5 changes to figure 4 through figure 9 ........................................... 9 changes to figure 10...................................................................... 10 changes to ordering guide .......................................................... 16 updated outline dimensions ....................................................... 16 8/05rev. 0 to rev. a changes to features, general description, and figure 1.............1 changes to table 1.............................................................................3 changes to table 2.............................................................................5 changes to figure 4...........................................................................9 changes to theory of operation section.................................... 12 changes to overview, throughput gain, and output dc offset control sections.................................................................. 13 renamed gain select section throughput gain section ........ 13 added composite video path gain section............................... 13 changes to table 6 and table 7 .................................................... 13 changes to figure 24 caption ...................................................... 14 changes to input and output coupling section........................ 14 added figure 25 and figure 26; renumbered sequentially ..... 14 changes to figure 27...................................................................... 15 1/05revision 0: initial version
aDA4410-6 rev. b | page 3 of 16 specifications v s = 5 v, @ t a = 25c, v o = 1.4 v p-p, g = 2, r l = 150 , unless otherwise noted. table 1. parameter test conditions/comments min typ max unit overall performance offset error input referred, all channels except cv 10 32 mv input referred, cv 12 40 mv max voltage across level1 and level2 inputs 500 mv input voltage range, all inputs v s? ? 0.1 v s+ ? 2.0 v output voltage swing, all outputs positive swing v s+ ? 0.35 v s+ ? 0.25 v negative swing v s? + 0.10 v s? + 0.3 v linear output current per channel 30 ma integrated voltage noise, referred to input all channels except cv 500 v rms filter input bias current all channels 6.6 15 a total harmonic distortion at 1 mhz f c = 36 mhz, f c = 18 mhz/f c = 9 mhz 0.01/0.07 % rgb/ypbpr channel dynamic performance ?1 db bandwidth cutoff frequency select = 36 mhz 31 mhz cutoff frequency select = 18 mhz 15 mhz cutoff frequency select = 9 mhz 8 mhz ?3 db bandwidth cutoff frequency select = 36 mhz 34 36 mhz cutoff frequency select = 18 mhz 16 18 mhz cutoff frequency select = 9 mhz 8 9 mhz out-of-band rejection f = 75 mhz ?33 ?42 db crosstalk f = 5 mhz, f c = 36 mhz ?68 db input mux isolation f = 1 mhz, r source = 300 86 db propagation delay f = 16 mhz, f c = 36 mhz 20.5 ns group delay variation cutoff frequency select = 36 mhz 9.5 ns cutoff frequency select = 18 mhz 16.5 ns cutoff frequency select = 9 mhz 29.5 ns y/c sd channel dynamic performance ?1 db bandwidth 7.5 mhz ?3 db bandwidth 8 9 mhz out-of-band rejection f = 27 mhz ?56 db propagation delay f = 1 mhz 72 ns group delay variation 30 ns crosstalk f = 1 mhz ?72 db input mux isolation f = 1 mhz, r source = 75 77 db y/c, cv output video performance differential gain ntsc 0.09 % differential phase ntsc 0.37 degrees control input performance input logic 0 voltage all inputs except disable 0.8 v input logic 1 voltage all inputs except disable 2.0 v input bias current all inputs except disable 7 15 a disable performance disable assert voltage v s+ ? 0.5 v disable assert time 100 ns disable deassert time 130 ns disable input bias current 12 20 a input-to-output isolationdisabled 100 db
aDA4410-6 rev. b | page 4 of 16 parameter test conditions/comments min typ max unit power supply operating range 4.5 12 v quiescent current 82 88 ma quiescent currentdisabled 15 150 a psrr, positive supply all channels except cv 62 72 db cv channel 59 66 db psrr, negative supply all channels except cv 55 62 db cv channel 52 56 db
aDA4410-6 rev. b | page 5 of 16 v s = 5 v, @ t a = 25c, v o = 1.4 v p-p, g = 2, r l = 150 , unless otherwise noted. table 2. parameter test conditions/comments min typ max unit overall performance offset error input referred, all channels except cv 14 33.5 mv input referred, cv 15 42.5 mv max voltage across level1 and level2 inputs 500 mv input voltage range, all inputs v s? ? 0.1 v s+ ? 2.0 v output voltage swing, all outputs positive swing v s+ ? 0.35 v s+ ? 0.25 v negative swing v s? + 0.3 v s? + 0.5 v linear output current per channel 30 ma integrated voltage noise, referred to input all channels except cv 500 v rms filter input bias current all channels 6.3 15 a total harmonic distortion at 1 mhz f c = 36 mhz, f c = 18 mhz/f c = 9 mhz 0.01/0.07 % rgb/ypbpr channel dynamic performance ?1 db bandwidth cutoff frequency select = 36 mhz 29 mhz cutoff frequency select = 18 mhz 15 mhz cutoff frequency select = 9 mhz 8 mhz ?3 db bandwidth cutoff frequency select = 36 mhz 33.0 35.5 mhz cutoff frequency select = 18 mhz 16.5 18 mhz cutoff frequency select = 9 mhz 8 9.5 mhz out-of-band rejection f = 75 mhz ?33 ?41.5 db crosstalk f = 5 mhz, f c = 36 mhz ?68 db input mux isolation f = 1 mhz, r source = 300 86 db propagation delay f = 5 mhz, f c = 36 mhz 21 ns group delay variation cutoff frequency select = 36 mhz 7.5 ns cutoff frequency select = 18 mhz 14 ns cutoff frequency select = 9 mhz 26 ns y/c sd channel dynamic performance ?1 db bandwidth 7.5 mhz ?3 db bandwidth 8 9 mhz out-of-band rejection f = 27 mhz ?57 db propagation delay f = 1 mhz 64 ns group delay variation 26 ns crosstalk f = 1 mhz ?72 db input mux isolation f = 1 mhz, r source = 75 77 db y/c, cv output video performance differential gain ntsc 0.11 % differential phase ntsc 0.25 degrees control input performance input logic 0 voltage all inputs except disable 0.8 v input logic 1 voltage all inputs except disable 2.0 v input bias current all inputs except disable 7 15 a disable performance disable assert voltage v s+ ? 0.5 v disable assert time 75 ns disable deassert time 125 ns disable input bias current 35 45 a input-to-output isolationdisabled 100 db
aDA4410-6 rev. b | page 6 of 16 parameter test conditions/comments min typ max unit power supply operating range 4.5 12 v quiescent current 86 93 ma quiescent currentdisabled 15 150 a psrr, positive supply all channels except cv 62 72 db cv channel 59 66 db psrr, negative supply all channels except cv 55 62 db cv channel 52 56 db
aDA4410-6 rev. b | page 7 of 16 absolute maximum ratings table 3. parameter rating supply voltage 12 v power dissipation see figure 2 storage temperature range C65c to +125c operating temperature range C40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, ja is specified for a device soldered in the circuit board with its exposed paddle soldered to a pad on the pcb surface that is thermally connected to a copper plane. table 4. thermal resistance package type ja jc unit 5 mm 5 mm, 32-lead lfcsp 43 5.1 c/w maximum power dissipation the maximum safe power dissipation in the aDA4410-6 package is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the aDA4410-6. exceeding a junction temperature of 150c for an extended time can result in changes in the silicon devices, potentially causing failure. the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ). the power dissipated due to load drive depends upon the particular application. for each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. the power dissipated due to all of the loads is equal to the sum of the power dissipations due to each individual load. rms voltages and currents must be used in these calculations. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads from metal traces, through-holes, ground, and power planes, reduces the ja . the exposed paddle on the underside of the package must be soldered to a pad on the pcb surface that is thermally connected to a copper plane to achieve the specified ja . figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 32-lead lfcsp (43c/w) on a jedec standard 4-layer board with the underside paddle soldered to a pad that is thermally connected to a pcb plane. ja values are approximations. 1.0 1.5 2.0 2.5 3.0 3.5 4.5 4.0 ?40 ?20 0 20 40 60 lfcsp 80 05265-002 ambient temperature (c) maximum power dissipation (w) figure 2. maximum power dissipation vs. temperature for a 4-layer board esd caution esd (electrostatic discharge) sensitive device. electr ostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
aDA4410-6 rev. b | page 8 of 16 pin configuration and fu nction descriptions 05265-003 1 8 24 25 32 16 9 17 pin 1 indicator aDA4410-6 (not to scale) figure 3. 32-lead lfcsp pi n configuration, top view table 5. pin function descriptions pin no. mnemonic description 1 pb1/b1_hd channel 1 pb/b high definition input 2 gnd signal ground reference 3 pr1/r1_hd channel 1 pr/r high definition input 4 f_sel_a filter cutoff select input a 5 f_sel_b filter cutoff select input b 6 y2/g2_hd channel 2 y/g high definition input 7 gnd signal ground reference 8 pb2/b2_hd channel 2 pb/b high definition input 9 gnd signal ground reference 10 pr2/r2_hd channel 2 pr/r high definition input 11 mux_sd standard definition input mux select line 12 y1_sd channel 1 y standard definition input 13 y2_sd channel 2 y standard definition input 14 c1_sd channel 1 c standard definition input 15 c2_sd channel 2 c standard definition input 16 vcc positive power supply 17 vee negative power supply 18 cv_out composite video output 19 c_sd_out c standard definition output 20 y_sd_out y standard definition output 21 g_sel gain select 22 pr/r_hd_out pr/r high definition output 23 pb/b_hd_out pb/b high definition output 24 y/g_hd_out y/g high definition output 25 vee negative power supply 26 vcc positive power supply 27 disable disable/power down/logic reference 28 level2 dc level adjust pin 2 29 level1 dc level adjust pin 1 30 mux_hd high definition input mux select line 31 y1/g1_hd channel 1 y/g high definition input 32 gnd signal ground reference
aDA4410-6 rev. b | page 9 of 16 typical performance characteristics unless otherwise noted, g = 2, r l = 150 , v o = 1.4 v p-p, v s = 5 v, t a = 25c. 9 ?48 ?45 ?42 ?39 ?36 ?33 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 1 10 100 05265-004 frequency (mhz) gain (db) black lines: v s = +5v gray lines: v s =5v f c = 9mhz f c = 18mhz f c = 36mhz figure 4. frequency response vs. power supply and cutoff frequency (g = 2) 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 1 10 100 05265-005 frequency (mhz) gain (db) black lines: v s = +5v gray lines: v s =5v f c = 9mhz f c = 18mhz f c = 36mhz figure 5. frequency response flat ness vs. cutoff frequency (g = 2) 9 ?45 ?48 ?42 ?39 ?36 ?33 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 1 10 100 05265-053 frequency (mhz) gain (db) black lines: v o = 2v p-p gray lines: v o = 0.1v p-p f c = 9mhz f c = 18mhz f c = 36mhz figure 6. frequency response vs. cu toff frequency and output amplitude 9 12 15 ?45 ?42 ?39 ?36 ?33 ?30 ?27 ?24 ?21 ?18 ?15 ?12 ?9 ?6 ?3 0 3 6 1 10 100 05265-006 frequency (mhz) gain (db) black lines: v s = +5v gray lines: v s =5v f c = 9mhz f c = 18mhz f c = 36mhz figure 7. frequency response vs. power supply and cutoff frequency (g = 4) 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 1 10 100 05265-007 frequency (mhz) gain (db) black lines: v s = +5v gray lines: v s =5v f c = 9mhz f c = 18mhz f c = 36mhz figure 8. frequency response flat ness vs. cutoff frequency (g = 4) 9 6 3 0 ?3 ?6 ?9 ?12 ?15 ?18 ?21 ?24 ?27 ?30 ?33 ?36 ?39 ?42 ?45 ?48 1 100 10 05265-017 frequency (mhz) gain (db) f c = 9mhz f c = 18mhz f c = 36mhz red lines: +85c green lines: +25c blue lines: ?40c figure 9. frequency response vs. temperature and cutoff frequency
aDA4410-6 rev. b | page 10 of 16 100 90 80 70 60 50 40 30 20 10 1 10 100 05265-008 frequency (mhz) group delay (ns) black lines: v s = +5v gray lines: v s =5v f c = 9mhz f c = 18mhz f c = 36mhz figure 10. group delay vs. frequency, power supply, and cutoff frequency ? 40 ?110 ?100 ?90 ?80 ?70 ?60 ?50 0.1 1 100 10 05265-018 frequency (mhz) crosstalk referred to input (db) f c = 9mhz f c = 18mhz f c = 36mhz r source = 300 ? y1, pb1 source channels pr1 receptor channel figure 11. hd channel crosstalk vs . frequency and cutoff frequency ? 40 ?110 ?100 ?90 ?80 ?70 ?60 ?50 0.1 1 100 10 05265-013 frequency (mhz) mux isolation referred to input (db) r source = 300 ? unselected mux is driven f c = 36mhz f c = 18mhz f c = 9mhz figure 12. hd mux isolation vs. frequency and cutoff frequency ? 60 ?110 ?105 ?100 ?95 ?90 ?85 ?80 ?75 ?70 ?65 01 4 3 2 05265-020 frequency (mhz) noise (db) 5 bandwidth 100khz to 4.2mhz ntc-7 weight figure 13. cv noise spectrum ? 40 ?110 ?100 ?90 ?80 ?70 ?60 ?50 0.1 1 100 10 05265-019 frequency (mhz) crosstalk referred to input (db) r source = 300 ? mux input 2 selected y1, c1 source channels y2 receptor channel c2 source channel y2 receptor channel figure 14. sd channel crosstalk vs. frequency ? 40 ?110 ?100 ?90 ?80 ?70 ?60 ?50 0.1 1 100 10 05265-014 frequency (mhz) mux isolation referred to input (db) unselected mux is driven r source = 300 ? r source = 75 ? figure 15. sd mux isolation vs. frequency and source resistance
aDA4410-6 rev. b | page 11 of 16 ? 5 ?75 ?65 ?55 ?45 ?35 ?25 ?15 0.1 1 100 10 05265-015 frequency (mhz) psrr referred to input (db) f c = 9mhz f c = 18mhz f c = 36mhz ? 5 ?75 ?65 ?55 ?45 ?35 ?25 ?15 0.1 1 100 10 05265-016 frequency (mhz) psrr referred to input (db) f c = 9mhz f c = 18mhz f c = 36mhz figure 16. positive supply psrr vs . frequency and cutoff frequency figure 19. negative supply psrr vs . frequency and cutoff frequency 3.5 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 05265-009 output voltage (v) 200ns/div f c = 9mhz f c = 36mhz f c = 18mhz 05265-011 output voltage (v) 200ns/div f c = 9mhz f c = 36mhz f c = 18mhz g = 4 v o = 1.4v p-p 3.5 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 figure 17. transient response vs. cutoff frequency (g = 2) figure 20. transient response vs. cutoff frequency (g = 4) t = 0 05265-010 output voltage (v) 50ns/div error = 2 input ? output (0.5%/div) 0.5% (65ns) output 2 input 1% (57ns) 3.5 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 6 5 4 3 2 1 0 ?1 05265-012 output voltage (v) 200ns/div f c = 9mhz 2 input voltage f c = 18mhz f c = 36mhz figure 21. overdrive reco very vs. cutoff frequency figure 18. settling time 05265-051 minimum-loss matching network loss calibrated out 50 ? 118? r l = 150 ? 50 ? 86.6 ? 50 ? network analyzer tx network analyzer rx dut figure 22. basic test circuit for swept frequency measurements
aDA4410-6 rev. b | page 12 of 16 theory of operation the aDA4410-6 is an integrated video filtering and driving solution that offers variable bandwidth to meet the needs of several different video formats. there are a total of five filter sections, three for component video and two for y/c and composite video. the component video filters have switchable bandwidths for standard definition interlaced, progressive, and high definition systems. the y/c channels have fixed 9 mhz, 3 db cutoff frequencies and include a summing circuit that feeds an additional buffer for a composite video output. each filter section has a sixth-order butterworth response that includes group delay optimization. the group delay variation from 100 khz to 36 mhz in the 36 mhz section is 8 ns, which produces a fast settling pulse response. the aDA4410-6 is designed to operate in many different video environments. the supply range is 5 v to 12 v, single supply or dual supply, and requires a relatively low quiescent current of 15 ma per channel. in single-supply applications, the psrr is greater than 70 db, providing excellent rejection in systems with supplies that are noisy or under-regulated. in applications where power consumption is critical, the part can be powered down to draw 15 a by pulling the disable pin to the most positive rail. the aDA4410-6 is also well suited for high encoding frequency applications because it maintains a stop- band attenuation of 50 db beyond 200 mhz. the aDA4410-6 is intended to take dc-coupled inputs from an encoder or other ground-referenced video signals. the aDA4410-6 input is high impedance. no minimum or maximum input termination is required, though input terminations above 1 k can degrade crosstalk performance at high frequencies. no clamping is provided internally. for applications where dc restoration is required, dual supplies work best. using a termination resistance of less than a few hundred ohms to ground on the inputs and suitably adjusting the level shift circuitry provides precise placement of the output voltage. for single-supply applications (v s? = gnd), the input voltage range extends from 100 mv below ground to within 2.0 v of the most positive supply. each filter section has a 2:1 input multiplexer that includes level-shifting circuitry. the level- shifting circuitry adds a dc component to ground-referenced input signals so that they can be reproduced accurately without the output buffers hitting the negative rail. because the filters have negative rail input and rail-to-rail output, dc level shifting is generally not necessary, unless accuracy greater than that of the saturated output of the driver is required at the most negative edge. this varies with load but is typically 100 mv in a dc- coupled, single-supply application. if ac coupling is used, the saturated output level is higher because the drivers have to sink more current on the low side. if dual supplies are used (v s? < gnd), no level shifting is required. in dual-supply applications, the level shifting circuitry can be used to take a ground-referenced signal and put the blanking level at ground while the sync level is below ground. the output drivers on the aDA4410-6 have rail-to-rail output capabilities. they provide either 6 db or 12 db of gain with respect to the ground pins. gain is controlled by the external gain select pin. each output is capable of driving two ac- or dc- coupled 75 source-terminated loads. if a large dc output level is required while driving two loads, ac coupling should be used to limit the power dissipation. input mux isolation is primarily a function of the source resistance driving into the aDA4410-6. higher resistances result in lower isolation over frequency, while a low source resistance, such as 75 , has the best isolation performance. in the sd channels, the isolation variation is most pronounced due to the stray capacitance that exists between the adjacent input pins. the hd input pins are not adjacent; therefore, this effect is less pronounced on the hd channels. see figure 15 for a performance comparison of the different source resistances feeding the sd inputs.
aDA4410-6 rev. b | page 13 of 16 applications overview with its high impedance multiplexed inputs and high output drive, the aDA4410-6 is ideally suited to video reconstruction and antialias filtering applications. the high impedance inputs give designers flexibility with regard to how the input signals are terminated. devices with dac current source outputs that feed the aDA4410-6 can be loaded in whatever resistance provides the best performance, and devices with voltage outputs can be optimally terminated as well. the aDA4410-6 outputs can each drive up to two source-terminated 75 loads and can therefore directly drive the outputs from set-top boxes, dvd players, and the like without the need for a separate output buffer. binary control inputs are provided to select cutoff frequency, throughput gain, and input signal. these inputs are compatible with 3 v and 5 v ttl and cmos logic levels, referenced to gnd. the disable feature is asserted by pulling the disable pin to the positive supply. the level1 and level2 inputs comprise a differential input that controls the dc level at the output pins. multiplexer select inputs selection between the two multiplexer inputs is controlled by the logic signals applied to the mux_sd and mux_hd inputs. the mux_sd input controls the standard definition (sd) inputs, and the mux_hd input controls the high definition (hd) inputs. table 6 summarizes the multiplexer operation. throughput gain the throughput gain of the aDA4410-6 signal paths can be 2 or 4. gain selection is controlled by the logic signal applied to the g_sel pin. table 6 summarizes how the gain is selected. composite video path gain the composite video signal is produced by passively summing the c and v outputs (see figure 1 ), which have been amplified by their respective gain stages. each signal experiences a 6 db loss as it passes through the passive summer and is subsequently amplified by 6 db in the fixed 2 stage following the summer. the net signal gain through the composite video path is therefore 0 db, and the resulting composite signal present at the aDA4410-6 output is the sum of y and c with unity gain. the offset voltage at the composite video output is twice that of the offset on the y or c outputs because the offsets on the y and c outputs are the same and appear as a common-mode input to the summer. the voltage between the summing resistors due to the offset voltages is therefore equal to the output offset voltage on the y and c outputs and appears at the composite video output with a gain of 2 after passing through the fixed 2 gain stage. disable the aDA4410-6 includes a disable feature that can be used to save power when a particular device is not in use. as indicated in the overview section, the disable feature is asserted by pulling the disable pin to the positive supply. table 6 summarizes the disable feature operation. the disable pin also functions as a reference level for the logic inputs and, therefore, must be connected to ground when the device is not disabled. table 6. logic pin function description disable mux_hd mux_sd g_sel v s+ = disabled 1 = hd channel 1 selected 1 = sd channel 1 selected 1 = 4 gain gnd = enabled 0 = hd channel 2 selected 0 = sd channel 2 selected 0 = 2 gain cutoff frequency selection four combinations of cutoff frequencies are provided for the hd video signals. the cutoff frequencies were selected to correspond with the most commonly deployed hd scanning systems. selection between the cutoff frequency combinations is controlled by the logic signals applied to the f_sel_a and f_sel_b inputs. table 7 summarizes cutoff frequency selection. table 7. filter cutoff frequency selection f_sel_a f_sel_b y/g cutoff pb/b cutoff pr/r cutoff 0 0 36 mhz 36 mhz 36 mhz 0 1 36 mhz 18 mhz 18 mhz 1 0 18 mhz 18 mhz 18 mhz 1 1 9 mhz 9 mhz 9 mhz output dc offset control the level1 and level2 inputs work as a differential input- referred output offset control. in other words, the output offset voltage of a given channel (with the exception of the cv channel) is equal to the difference in voltage between the level1 and level2 inputs multiplied by the overall filter gain. this relationship is expressed in equation 1. v os ( out ) = ( level1 ? level2 )(g ) (1) where: level1 and level2 are the voltages applied to the respective inputs. g is throughput gain. for example, with the g_sel input set for 2 gain, setting level1 to 300 mv and level2 to 0 v shifts the offset voltages at the aDA4410-6 outputs to 600 mv. this particular setting can be used in most single-supply applications to keep the output swings safely above the negative supply rail.
aDA4410-6 rev. b | page 14 of 16 as previously discussed, the composite video output is developed by passively summing the y and c outputs that have passed through their respective output gain stages, then multiplying this sum by a factor of two to obtain the output (see figure 1 ). the offset of this output is equal to 2 that of the other outputs. because of this, in many cases, it is necessary to ac-couple the cv output or ensure that it is connected to an input that is ac- coupled. this is generally not an issue because it is common practice to employ ac coupling on composite video inputs. the maximum differential voltage that can be applied across the level1 and level2 inputs is 500 mv. from a single-ended standpoint, the level1 and level2 inputs have the same range as the filter inputs. see the specifications tables for the limits. the level1 and level2 inputs must each be bypassed to gnd with a 0.1 f ceramic capacitor. in single-supply applications, a positive output offset must be applied to keep the negative-most excursions of the output signals above the specified minimum output swing limit. figure 23 and figure 24 illustrate several ways to use the level1 and level2 inputs. figure 23 shows an example of how to generate fully adjustable level1 and level2 voltages from 5 v and single +5 v supplies. these circuits show a general case, but a more practical approach is to fix one voltage and vary the other. figure 24 illustrates an effective way to produce a 600 mv output offset voltage in a single-supply application. although the level2 input could simply be connected to gnd, figure 24 includes bypassed resistive voltage dividers for each input so that the input levels can be changed, if necessary. additionally, many in-circuit testers require that i/o signals not be tied directly to the supplies or gnd. dnp indicates do not populate. 05265-048 dual supply 0.1f level1 9.53k ? 1k? 9.53k ? +5v ?5v 0.1f level2 9.53k ? 1k? 9.53k ? +5v ?5v single supply 0.1f level1 1k? 9.09k ? +5v 0.1f level2 1k? 9.09k ? +5v figure 23. generating fully adjustable output offsets 05265-049 0.1 f level1 634 10k +5v dnp level2 0 dnp +5v figure 24. flexible circuits to set the level1 and level2 inputs to obtain a 600 mv output offset on a single supply (g = 2) input and output coupling inputs to the aDA4410-6 are normally dc-coupled. ac coupling the inputs is not recommended; however, if ac coupling is necessary, suitable circuitry must be provided following the ac coupling element to provide proper dc level and bias currents at the aDA4410-6 input stages. the aDA4410-6 outputs can be either ac- or dc-coupled. as discussed in the output dc offset control section, the cv output offset is different from the other outputs, and the cv output is generally ac-coupled. when driving single ac-coupled loads in standard 75 video distribution systems, 220 f coupling capacitors are recommended for use on all but the chrominance signal output. because the chrominance signal is a narrow-band modulated carrier, it has no low frequency content and can therefore be coupled with a 0.1 f capacitor. there are two ac coupling options when driving two loads from one output. one is to simply use the same value capacitor on the second load, while the other is to use a common coupling capacitor that is at least twice the value used for the single load (see figure 25 and figure 26 ). 0 5265-054 75 ? 75 ? 75? cable 75? cable 220f 220f 75? 75? figure 25. driving two ac-coupled loads with two coupling capacitors 05265-055 75 ? cable 75 ? cable 75? 75? 75? 75? 470f figure 26. driving two ac-coupled lo ads with one common coupling capacitor
aDA4410-6 rev. b | page 15 of 16 printed circuit board layout when the aDA4410-6 receives its inputs from a device with current outputs, the required load resistor value for the output current is often different from the characteristic impedance of the signal traces. in this case, if the interconnections are sufficiently short (<< 0.1 wavelength), the trace does not have to be terminated in its characteristic impedance. figure 27 shows an example in which the aDA4410-6 input originates from dacs that require 300 load resistors. traces of 75 can be used in this instance, provided their lengths are an inch or two at the most. this is easily achieved because the aDA4410-6 and the device feeding it are usually adjacent to each other, and connections can be made that are less than one inch in length. as with all high speed applications, attention to printed circuit board layout is of paramount importance. standard high speed layout practices should be adhered to when designing with the aDA4410-6. a solid ground plane is recommended, and surface-mount ceramic power supply decoupling capacitors should be placed as close as possible to the supply pins. all of the aDA4410-6 gnd pins should be connected to the ground plane with traces that are as short as possible. controlled impedance traces of the shortest length possible should be used to connect to the signal i/o pins and should not pass over any voids in the ground plane. a 75 impedance level is typically used in video applications. all signal outputs of the aDA4410-6 should include series termination resistors when driving transmission lines. video encoder reconstruction filter the aDA4410-6 is easily applied as a reconstruction filter at the dac outputs of a video encoder. figure 27 illustrates how to use the aDA4410-6 in this type of application with an adv7314 video encoder in a single-supply application with ac-coupled outputs. 2.5v (analog) 2.5v (digital) 2.5v/3.3v (digital i/o) 5v (analog) device address select comp1 comp2 v dd_io i 2 c i 2 c bus ad1580 v ref v aa v dd y9?y0 c9?c0 s9?s0 sclk sda alsb dac a dac b dac c dac d dac e dac f r set2 r set1 ext_lf note: each power supply pin must have its own decoupling network 1 44 43 42 39 38 37 47 35 10, 56 36 45 41 46 33 34 2-9, 12, 13 14-18, 26-30 51-55, 58-62 20 21 22 adv7314 clkin_a clkin_b 32 63 p_hsync p_vsync p_blank s_hsync s_vsync s_blank 23 24 25 50 49 48 agnd dgnd gnd_io 64 11, 57 40 19 rtc_scr_tr 31 nc 12 y1_sd y2_sd 13 c1_sd c2_sd 14 15 y1/g1_hd y2/g2_hd 31 6 pb1/b1_hd pb2/b2_hd 1 8 pr1/r1_hd pr2/r2_hd 3 10 level1 level2 vcc 16 29 28 g_sel 21 disable 27 mux_sd 11 mux_hd 30 f_sel_a 4 f_sel_b 5 20 y_sd_out 19 c_sd_out 18 cv_out gnd 2, 7, 9, 32 vee 17, 25 24 y/g_hd_out 23 pb/b_hd_out 22 pr/r_hd_out 26 vcc channel 2 video inputs binary control inputs aDA4410-6 multifunctional input sync and blanking signals pixel clocks digital video buses 75 ? 220f 75 ? 220f 75 ? 220f 75 ? 0.1f 75 ? 220f 75 ? 220f 300 ? 300 ? 300 ? 300 ? 300 ? 3.04k ? 3.04k ? 100 ? 100 ? reset reset dnp* *do not populate 0? 634 ? 10k ? 5k ? 5k ? 5k ? 5k ? 0.1f dnp* 0.1f 0.1f 0.01f 0.01f 0.1f 0.1f 0.1f 0.1f 820pf 3.5pf 0.01f 0.1f 4.7f + 0.1f 1.1k ? 4.7k ? 4.7k ? 0 5265-050 figure 27. the aDA4410-6 applied as a reconstruction filter following the adv7314
aDA4410-6 rev. b | page 16 of 16 outline dimensions compliant to jedec standards mo-220-vhhd-2 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane coplanarity 0.08 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indicator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) figure 28. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model temperature range package description package option ordering quantity aDA4410-6acpz-r2 1 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 250 aDA4410-6acpz-r7 1 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 1,500 aDA4410-6acpz-rl 1 C40c to +85c 32-lead lead frame chip scale package (lfcsp_vq) cp-32-2 5,000 t 1 z = pb-free part. ? 2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05265C0C3/06(b) ttt

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